1. Field of the Invention
The present invention relates generally to methods and systems for fabricating microelectronic fabrication products. More particularly, the present invention relates to methods and systems for estimating microelectronic fabrication product yield when fabricating microelectronic fabrication products.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Desirable in the art of microelectronic fabrication for use when fabricating microelectronic fabrications are methods and systems for determining microelectronic fabrication product yield when fabricating microelectronic fabrication products. Methods and systems for determining microelectronic fabrication product yield when fabricating microelectronic fabrication products are desirable in the art of microelectronic fabrication insofar as such methods and systems in turn provide useful information which may be employed for: (1) projecting microelectronic fabrication substrate starts needed to fill a microelectronic fabrication product order; (2) accurately quoting the microelectronic fabrication product order; and (3) accurately forecasting a microelectronic fabrication facility utilization rate when fabricating a microelectronic fabrication product.
While methods and systems for determining microelectronic fabrication product yield when fabricating microelectronic fabrication products are thus clearly desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, methods and systems for determining microelectronic fabrication product yield when fabricating microelectronic fabrication products are nonetheless not entirely without problems in the art of microelectronic fabrication. In that regard, methods and systems for determining microelectronic fabrication product yield when fabricating microelectronic fabrication products are not often readily implemented in the art of microelectronic fabrication insofar as they are often dependent upon complex, cumbersome and intricate microelectronic fabrication product yield modeling equations.
It is thus desirable in the art of microelectronic fabrication to provide methods and systems for accurately and efficiently estimating microelectronic fabrication product yields when fabricating microelectronic fabrication products.
It is towards the foregoing object that the present invention is directed.
Various methods and systems have been disclosed in the art of microelectronic fabrication for estimating microelectronic fabrication product yield when fabricating microelectronic fabrication products.
Included among the methods and systems, but not limited among the methods and systems, are methods and systems disclosed within: (1) Komatsuzaki et al., in U.S. Pat. No. 5,754,432 (a method and a system for estimating microelectronic fabrication product yield, where the method and the system are predicated upon presumed levels of ambient particles deposited upon microelectronic fabrication substrates when fabricating microelectronic fabrication products); and (2) Heavlin et al., in U.S. Pat. No. 5,946,214 (a computer implemented method for estimating microelectronic fabrication product yield when fabricating, in particular, microelectronic fabrication products having designed and fabricated therein redundancy circuits).
Desirable in the art of microelectronic fabrication are additional methods and systems which may be employed for efficiently estimating microelectronic fabrication product yields when fabricating microelectronic fabrication products.
It is towards the foregoing object that the present invention is directed.